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Title: Python extension for a convolution neural network accelerator
Authors: Pattanapong Khaopaibul Wu Jing Han
Keywords: Engineering::Electrical and electronic engineering::Microelectronics
Engineering::Electrical and electronic engineering::Computer hardware, software and systems
Issue Date: 2022
Publisher: Nanyang Technological University
Source: Pattanapong Khaopaibul Wu Jing Han (2022). Python extension for a convolution neural network accelerator. Final Year Project (FYP), Nanyang Technological University, Singapore.
Project: B2055-211
Abstract: With the advent of artificial intelligence, machine learning, and deep learning, comes numerous possible possibilities for their applications. Neural networks that can self-learn is of particular importance. Convolutional Neural Networks (CNN) are one such neural network that has made significant strides. Image classification, recognition, object detection, and many other applications have seen a rise in our everyday lives, yet more can be done. Powering these networks through traditional hardware accelerators like our everyday graphical processing units (GPUs) prove powerful and efficient, but not portable. Field Programmable Gate Arrays (FPGA) are a type of hardware accelerator that has shown promise in delivering powerful computational capabilities that mesh well with the architecture of CNNs. To capitalise on their strengths, this report aims to document the seamless porting of architecture from a user-friendly Python environment directly to FPGAs for fast implementation.
Schools: School of Electrical and Electronic Engineering 
Organisations: Institute of Microelectronics, A*STAR
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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