High-speed intelligent power converter IC

Abstract

Switched-mode DC-DC converter (power converter) is an important electronic circuit to perform the voltage conversion in electronic devices. Switched-mode DC-DC converter architectures generally have a feedback loop for output regulation. An important part of the loop is the output inductor of the converter as its value may determine the loop stability. The value of the inductor, however, has to be chosen conservatively as it generally determines the size of the converter. Fully-integrated converters, where the inductor is integrated either on the IC or within the IC package, are increasingly popular for miniature and portable applications. To shrink the inductor size, the converter typically operates at high switching-frequencies (> 50 MHz).

Another important building block in the loop is the controller to sense output voltage variations and perform the necessary compensation. In high-speed converters, the controller and inductor design become challenging due to trade-offs in size, stability, and complexity (in part for which determine the power dissipation). For advanced converters, the controller operates digitally to perform desirable features, including complex compensation computation and possibly, intelligent compensation such as inductance value tuning/correction.

This report presents a high-speed digitally-controlled switched-mode DC-DC buck (step-down) converter design. The converter is designed to operate at a switching-frequency of 100 MHz, and with a 20 nH inductor and a 37.5 nF capacitor. The inductor is designed based on the square planar spiral coil geometry and to be implemented off-chip. The proposed digital controller architecture comprises of an analog-to-digital converter (ADC), a digital compensator, and a digital pulse-width modulator (DPWM), operating at the same switching-frequency.

For a high-speed digital controller design, reduced bits of operation are crucial. Higher switching activity occurs when utilizing more bits which is more error-prone. In the design, a 4-bit ADC and a 5-bit DPWM are achieved. An optimized design of the digital compensator is demonstrated. This optimization reduces the complexity of the conventional digital compensator with a decreased number of adders by 4 and multipliers by 5. Power dissipation of the optimized digital compensator is reduced by 82% compared to the conventional counterpart. Additionally, the proposed design achieves 88% power efficiency, 1.2 µs transient response, and 1% output voltage ripple. Multi-phase interleaving topology of the converter is presented with up to 92% output voltage ripple reduction and cancellation in output current ripple.