Design and verification for surface electrode openings of ion trap for scalable quantum computing

Abstract

Quantum computing is a promising candidate in the field of advanced computing. This technology is powerful as it reduces the computational time complexity of classical computers exponentially by applying the superposition principle. This project focuses on further improving the scalability and ion trapping efficiency by monolithically integrating photonics into the surface electrode ion trap itself. For designing the ion trap (planar Paul ion trap), we implement a symmetric 5-wire geometry. Dynamic electric field generated from two symmetric RF electrodes is used for ion confinement in radial plane, whereas DC electrodes are for control in axial direction. Trapped atomic ions are the basis in order to achieve high-fidelity quantum information processors and high-accuracy optical clocks. The concern of designing such ion traps is their scalability. Current state-of-the-art ion trap relies on free space optics for ion control, which limits portability and scalability. The integration of photonics for on-chip light routing is therefore of high interest. To perform this, an opening at the centre of the surface electrode is required to allow for light propagation. We demonstrate the modelling of ion traps with different openings design using COMSOL Multiphysics and evaluate the corresponding trapping performance, in particular the trapping height and trapping depth. We simulate through sweeping different locations for the opening (constant size of 20x20μm) along the axial direction. Observations done are mainly from the electric field distributions obtained from simulations. A trend in the plot is seen for each sweep location values. Similarly, we sweep through different opening sizes to investigate the ion trapping performance.