A buffer based low dropout regulator with fast transient response

Abstract

Low-dropout (LDO) voltage regulators are a widely-used device capable of regulating a stable supply voltage for electronic components in a system. Some components, particularly digital ones, are capable of pulling large amounts of current over a very short time. Hence, an LDO regulator with fast settling time and small spike voltage under load transients is required to ensure stable operation of the system.

The proposed LDO regulator, which is designed and simulated in Cadence Virtuoso using a 40nm CMOS process, operates at 1.1 V supply voltage and 0.9 V output. The proposed regulator employs a level-shifted flipped voltage follower structure with multiple AC- coupled feedback loops to provide fast transient response under the step load current. It employs an improved frequency compensation scheme.

The simulation results have shown that the output voltage overshoot and undershoot are 19.63 mV and 15.83 mV, respectively for a step load current of 0 mA to 50 mA with 200 ns edge time and 100 pF load capacitance. A 1% settling time of 568 ns was achieved.

With the proposed frequency compensation scheme, the regulator is capable of supporting load current between 0 mA and 50 mA while consuming only 22.68 µA quiescent current. This achieves lower quiescent current when compared to those of the representative prior- art works. More importantly, the performance of the regulator exhibits good transient FOMs, which are comparable to that of previously-reported works.

Finally, several possible areas of improvement, pertaining to the improvement of the open- loop DC gain and stability margins of the LDO regulator, are recommended.