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Title: Phase-locked loop for low frequency application using 0.18um CMOS technology
Authors: Zhang, Yao.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2009
Abstract: Over the past decade, the desirability of portable operation for all types of electronics system has grown tremendously. The requirement of portability thus places severe restriction on the IC size and power consumption. This leads to the need of scaling. To keep pace with the development of the mixed-signal design, a fully integrated Phase-Locked Loop frequency synthesizer operation with a supply voltage of 1.5 V is explored in this project. The emphasis of this project is the lower power and low frequency design of Phase-Locked Loop frequency synthesizer. It is implemented by integrating the phase-frequency detector, the charge-pump, the loop filter, voltage-controlled oscillator and frequency divider. In this report, the designed Voltage-Controlled Oscillator (VCO) is based on differential-ended ring oscillator. The requirement of VCO to operate at low frequency is the main reason of choosing the ring oscillator than LC topology. Ring oscillator could be designed to have low power consumption as it becomes the objective of this project. However, it suffers from low phase noise performance. The ring oscillator topology is designed to have wide swing voltage at the output in order to increase the phase noise performance. The designed frequency divider consists of three parts, Dual-Modulus Prescaler, Program Counter and Swallow Counter. Design of the frequency divider operates from 480 MHz to 496 MHz. With regards to system integration, system parameters and a 2nd order loop filter are designed for optimal performance. And layout considerations are also discussed.
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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