Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/158595
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dc.contributor.authorSu, Lingzhien_US
dc.date.accessioned2022-05-26T01:38:34Z-
dc.date.available2022-05-26T01:38:34Z-
dc.date.issued2022-
dc.identifier.citationSu, L. (2022). Hardware implementation of a power efficient CGRA with single-cycle multi-hop datapaths. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/158595en_US
dc.identifier.urihttps://hdl.handle.net/10356/158595-
dc.description.abstractCoarse-grained reconfigurable architectures (CGRAs) are computing architectures that provide word-level reconfigurability. CGRAs can achieve high throughput and high power efficiency, while maintaining post-fabrication computing flexibil- ity. In this dissertation, a 167-GOPS/W CGRA design with single-cycle multi- hop datapaths, named PACE, is proposed. The hardware architectures including processing element (PE), algorithm logic unit (ALU), routers, and on-chip pe- ripherals are presented. ALU input gating technique and no operation (NOP) clock gating technique are integrated with PEs to reduce power consumption of the ALU and PE module by 68.66% and 39.11%, respectively. In terms of hardware implementation, memory timing problem and combina- tional logic loop issue are discussed in this dissertation. Memory interface cir- cuit with buffer registers and inverted clock is introduced to static random ac- cess memory (SRAM) devices to achieve high speed and single-cycle latency. Constraints on combinational logic loop for flatten and hierarchy synthesis flows are respectively presented, to provide a detailed static timing analysis on the by- pass datapaths. Demonstrations based on FPGA and computer system are also provided, with successful running in applications such as the array add, general matrix multiplication (GEMM), and so on. A PACE chip is also successfully implemented on silicon at 100-MHz frequency.en_US
dc.language.isoenen_US
dc.publisherNanyang Technological Universityen_US
dc.subjectEngineering::Electrical and electronic engineering::Computer hardware, software and systemsen_US
dc.titleHardware implementation of a power efficient CGRA with single-cycle multi-hop datapathsen_US
dc.typeThesis-Master by Courseworken_US
dc.contributor.supervisorGoh Wang Lingen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Science (Electronics)en_US
dc.contributor.supervisoremailEWLGOH@ntu.edu.sgen_US
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