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|Title:||Design of an 8-bit 100-MS/s switched-capacitor DAC for quantum computing control||Authors:||Lyu, Changming||Keywords:||Engineering::Electrical and electronic engineering::Integrated circuits||Issue Date:||2022||Publisher:||Nanyang Technological University||Source:||Lyu, C. (2022). Design of an 8-bit 100-MS/s switched-capacitor DAC for quantum computing control. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/158600||Abstract:||Signal processing plays an important role in communication systems, control systems and computer systems. Signal processing tasks are generally implemented by digital signal processors, microcontrollers and microprocessors. However, signals in nature are analog signals, so digital-to-analog converter (DAC) has become indispensable as an interface between digital systems and the analog world. This dissertation analyzes the DAC of three common structures and designs an 8-bit 100MSPS CDAC by comparing the advantages and disadvantages of various structures. The design adopts a 4+4 segmentation method, which effectively reduces the area of the CDAC from a structural point of view. The design and layout of the circuit are performed in UMC40nm CMOS process. The function and performance of the DAC are verified using Cadence Spectre. At 1.2 V supply voltage, the single-ended output voltage swings from 0 V to 1.0 V and consuming 0.3 mA of quiescent power. Integral nonlinearity is less than 0.7 LSB, differential nonlinearity is less than 0.4 LSB. The spurious free dynamic range is about 53dB, signal to noise and distortion ratio is about 47.8dB and effective number of bits is 7.6bit when the input sinusoidal signal is 1.2695MHz with sampling clock of 100MHz. Bandgap can generate a voltage reference for CDAC. A sub-1v Bandgap was designed in this dissertation. It has low temperature coefficient (TC) and higher power supply rejection ratio (PSRR). And a start-up circuit is added in this Bandgap to ensure that Bandgap is working normally. To drive CDAC’s output for measurement, a high common mode input range (CMIR) op amp is designed in this dissertation. This op amp’s circuit adopts a 2-stage folded cascode. The input differential pairs are PMOS to ensure CMIR is from 0V to 1V. This op amp is also used in Bandgap.||URI:||https://hdl.handle.net/10356/158600||Schools:||School of Electrical and Electronic Engineering||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
Updated on Nov 29, 2023
Updated on Nov 29, 2023
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