Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/158948
Title: 8-order low-power digital FIR filter design
Authors: Shi, Yucen
Keywords: Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2022
Publisher: Nanyang Technological University
Source: Shi, Y. (2022). 8-order low-power digital FIR filter design. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/158948
Abstract: In recent years, the development of portable devices such as biomedical devices, Internet of things, wearable devices and mobile phones is faster and faster, with more and more powerful processing functions and faster running speed, which inevitably brings huge power consumption. Moreover, with the continuous reduction of process linewidth and the continuous increase of chip power density, however, there has been no breakthrough in battery technology. Therefore, the battery life ability has become an important reason restricting the development of these portable devices. Therefore, the development of low-power technology is imperative. In the direction of digital signal processing, digital filters are widely used because of their various advantages. Among them, FIR filters are particularly favored because of their linear phase characteristics, and are often used in medical devices such as hearing aids. Therefore, the study of FIR filter has a very broad application prospect. Based on the traditional digital FIR filter, this dissertation optimizes and improves its architecture, and finally designs an 8-order low-power digital FIR filter. Firstly, this dissertation introduces the development trend and difficulties of semiconductor integrated circuits, expounds the value of studying low-power technology, introduces the development of digital signal processing system, and analyzes the significance of designing digital filter. Secondly, this dissertation introduces the basic theory of digital filter design, the components, causes and calculation methods of digital circuit power consumption, and introduces some low-power technology methods from the design level. Then, based on the traditional architecture of digital FIR filter, this dissertation designs an 8-order low-power digital FIR filter, which uses a shift accumulation multiplier and a three-level pipelined parallel structure to reduce power consumption. Finally, combined with the simulation results of MATLAB and Modesim platform, it is verified that the function of the low-power digital FIR filter designed in this dissertation is correct, and can greatly reduce the power consumption by about 35% at most.
URI: https://hdl.handle.net/10356/158948
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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