Two dimensional materials-based multi gated devices and simulation

Abstract

In recent years, more and more research on the potential of two dimensional(2D) material based transistor have been published and widely studied. And one direction of the investigation of 2D material is multi-coplanar gates transistor. However, to study this kind of device more effectively, researchers need better technologies to simulate fabrication process and electrical performance of multi-coplanar gates transistor. In this research project, mechanical exfoliation has been used to prepare 2D semiconductors and electron beam lithography has been used to fabricate the samples of multi-coplanar gates transistors. And these transistors are used to verify the correct function of this kind of transistor. At the same time, a Sentaurus model of fabrication process and a HSPICE model of electrical performance are also built to simulate the performance of transistor in detail. And it is found that coplanar gates can effectively modulate carrier density of channel. And coplanar gates can be used to implement complex logic functions like addition. With the assistance of Sentaurus model’s simulation, gate length, distance between the channel and gate’s influence over digital logic of the transistor can be investigated, which reveals the potential of multi-coplanar gates transistor in the digital circuit design.