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Title: Siliconization of millimeter-wave to terahertz surface-plasmonic transceiver and phase-locked loops
Authors: Liang, Yuan
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2022
Publisher: Nanyang Technological University
Source: Liang, Y. (2022). Siliconization of millimeter-wave to terahertz surface-plasmonic transceiver and phase-locked loops. Doctoral thesis, Nanyang Technological University, Singapore.
Project: MOE2019-T2-1-114.
Abstract: The future 6G network and big-data center will be generating and capturing a wealth of data that was previously unimaginable. The conventional inter-server interconnects rely on optical cables that can reach Tera-scale; however, they are not fully based on integrated circuit (IC) processes and hence cannot be scaled down for both cost and power. Full integration in the complementary metal-oxide-semiconductor (CMOS) technologies has been identified as the ultimate solution to build the low-cost, low-power, highly compact interconnect that meets the stringent requirement of next generation 100/400 GbE communication. Unfortunately, silicon channels suffer from strong electromagnetic crosstalk (and loss) at high speed with limited output power generated by the signal source. To overcome such issues, conventional data interfaces have implemented crosstalk-compensated equalizers and signal source leading to an excessively high 5–20 pJ/bit power efficiency. Furthermore, crosstalk-compensated equalizers have limited speeds up to 13 Gb/s. Recently, the integrated surface plasmonic polaritons (SPPs) components and circuits were proposed and implemented in silicon at the ultra-broadband terahertz (THz) frequency toward high-speed, low-power, low-crosstalk signaling. The surface plasma (or surface wave) is a special electromagnetic (EM) wave to localize the free electron into the metal/medium interface, achieving extraordinary field confinement and enhancement. Implemented in advanced CMOS technologies, the design will be smaller, lighter, cheaper, and scalable for emerging applications such as low-crosstalk digital signaling, ultra-high-speed communication, low-power transceiver, remote sensing, and threat detection. As there is a lack of knowledge on how to achieve surface plasmonic generation, transmission, modulation, conversion, and amplification in silicon, this thesis aims to conceptualize, design, implement, and validate several on-chip high-performance metadevices. Several I/O interface architectures are reviewed in Chapter 2, followed by the introduction of SPPs fundamentals, design, and comparison to conventional on-chip transmission lines. The impact of channel crosstalk on bit-error rate (BER) as well as power consumption will be evaluated based on link budget analysis. To evaluate how plasmonic can attenuate the channel crosstalk, the surface wave transmission lines (T-line) are modeled on the T-section network incorporated by the lossy T-line model. This model can also describe the impedance, phase shift, dispersion behavior, and loss of the surface plasmonic T-line from the circuit’s perspective. Like other surface plasmonic T-lines implemented on the printed circuit boards (PCBs), impedance or momentum mismatch occurs between the TEM devices and the plasmonic devices. A gradient groove plasmonic converter is designed and experimentally verified in Chapter 3. Since the coplanar waveguide (CPW) is not involved for impedance conversion, the design is compact and therefore suitable for on-chip implementation. A split-ring-resonator-based (SRR-based) amplitude modulator and a D-band signal source are proposed in Chapter 4. The modulator is designed in a vertical fashion, occupying only 0.002 mm2 of silicon area without consuming static power. By mutually neutralizing the residual electrical field (E-field) along the main SRR lane body with enforcement to the magnetic field, the SRR-based modulator effectively minimizes the skin and proximity effects that are commonly observed for CMOS top metals. Such an effort to cancel the residual current leads to a significant boost of the quality factor (Q-factor), which was measured to be 83. Moreover, as the magnetic resonance frequency is sensitive to the ring slit of SRRs, high-ON-OFF-ratio modulation is attained by altering the status of the ring slits. Using such a high-Q SRR, a high-output power source is proposed for D-band signal generation. To boost the output power at D-band, four oscillator unit cells are self-synchronized in a closed-loop for effective power combining, forming a coupled oscillator network (CON). The tank resonator combines both the split-ring resonator (SRR) and plasmonic T-line for high output power within a minimal area due to the high-Q of SRR and the low-wave effect of the plasmonic T-line. Using the above mentioned metadevices, in Chapter 5, a 140-GHz dual-channel on–off keying (OOK) I/O transceiver is proposed and implemented in a 65-nm CMOS technology, delivering 13.5 Gb/s, crosstalk-immune data with 2.6 pJ/bit/lane energy efficiency. The above endeavors pave the way toward multi-channel yet crosstalk-immune, chip-to-chip data communication. However, the adopted OOK scheme has a low spectral efficiency. Communication schemes such as binary phase shift keying (BPSK), frequency-shift keying (FSK), or frequency division multiplexing (FDM) have higher spectral efficiency, but they require a smaller signal-to-noise ratio (SNR) to achieve a certain BER. Moreover, these communication schemes necessitate a stable, precise, and robust frequency control circuit for coherent data recovery. These requirements have motivated the design of low-jitter and low-reference-spur millimeter wave (mm-wave) and THz phase-locked loops (PLLs), which are another contribution of this thesis. Traditional charge-pump PLLs (CP-PLLs) are widely used in various high-frequency communication and radar systems, but the high phase noise of charge pumps (CPs) commonly dominates the in-band phase noise of PLLs, degrading the integrated jitter. State-of-the-art PLLs exploiting sub-sampling and sub-harmonically injection-locked techniques substantially suppress the in-band phase noise of the phase detectors (PDs), achieving < 100 fsrms integrated jitter, but with worse reference spurs of ~ –50 dBc. This thesis aims to provide several design approaches to break the tradeoff between the reference spur reduction and the level of rejection to the voltage-controlled oscillator (VCO) phase noise. Several phase detectors, namely quadrature sampling PD (QSPD), spur-compensation PD (SCPD), and quadrature XOR-gate (QXOR) technique, are proposed to suppress the PLL reference spurs while maintaining the high PD gain for sufficiently attenuating the PD phase noise. The proposed PDs attenuate the PLL reference spur without reducing the PLL loop bandwidth, and thus they do not affect the level of suppression of VCO phase noise. For this reason, low-reference-spur and low-jitter can be achieved concurrently. Two 40-GHz CMOS PLLs achieving < –60 dBc reference spur with < 130 fsrms integrated jitter (10 kHz to 100 MHz) are described in detail in Chapter 6. A low-reference-spur and low-jitter 320-GHz Silicon Germanium (SiGe) BiCMOS signal source using the proposed QXOR PD is introduced in Chapter 7. The proposed 320-GHz PLL achieves –73 dBc reference spur and recorded 122 fsrms integrated jitter (10 kHz-to-100 MHz), while obtaining a –3.3 dBm probed output power for a single signal source unit cell, demonstrating state-of-the-art performance for many emerging THz applications.
Schools: School of Electrical and Electronic Engineering 
Research Centres: VIRTUS, IC Design Centre of Excellence 
Rights: This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License (CC BY-NC 4.0).
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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