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Title: 32-bit low power-delay-product arithmetic-logic unit design
Authors: Ren, Jialu
Keywords: Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2022
Publisher: Nanyang Technological University
Source: Ren, J. (2022). 32-bit low power-delay-product arithmetic-logic unit design. Master's thesis, Nanyang Technological University, Singapore.
Abstract: Arithmetic-logic unit (ALU) is a combinational logic circuit that can realize arithmetic and logic operations. Most arithmetic logic units can perform the following operations: integer arithmetic operations (subtraction, addition), bit logic operations (AND, OR, XOR, NOR), shift operations (left shift, right shift). For the Arithmetic-logic unit (ALU), the adder is the core unit of its arithmetic operation. The performance of the adder has a great impact on the performance of the entire arithmetic unit, and its operation speed directly affects the speed of the ALU. This project finished the design of a basic 32-Bit ALU and also did some optimization to achieve a low Power-Delay-Product ALU. The main optimizations are using Carry-Look-Ahead Adder to reduce the delay of critical path and convert subtraction to complement addition to realize reusing of adders. After using Verilog to finish the circuit design, the simulation, synthesis and power simulation are finished with the help of simulation tools such as DVE and Design Compiler, using STM065 library. The simulation result shows that although the power dissipation of the proposed ALU is marginally (6%) higher power dissipation than the traditional ALU, it has a significantly (60%) lower delay than the traditional RCA ALU, with an overall PDP of 57% lower than the traditional ALU.
Schools: School of Electrical and Electronic Engineering 
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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