Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/159456
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dc.contributor.authorDu, Yifanen_US
dc.date.accessioned2022-06-20T04:48:06Z-
dc.date.available2022-06-20T04:48:06Z-
dc.date.issued2022-
dc.identifier.citationDu, Y. (2022). LTspice implementation of PKU compact model of metal-oxide-based RRAM: part C_simulation of RRAM memory arrays. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/159456en_US
dc.identifier.urihttps://hdl.handle.net/10356/159456-
dc.description.abstractRRAM, which has the characteristics of high speed, low power consumption, easy integration, compatibility with CMOS technology, is a potential NVM technology. It is considered as the next-generation high density storage and high-performance computing technology, and also, a powerful alternative of flash memory technology. In this dissertation, we first briefly reviewed several mainstream memory technologies, including the volatile memory (or random access memory) technologies represented by SRAM and DRAM and the non-volatile memory technology represented by flash memory. Aiming at many shortcomings of flash technology, we listed three NMV technologies which are considered as alternatives to traditional NAND and NOR flash memory, including PCRAM, STT-MRAM and RRAM. In chapter 2, we discussed the basic principles of RRAM, especially the memristor, which is a fourth class of electrical circuit, joining the resistor, the capacitor, and the inductor. Also we briefly analyzed how different memristor or electrode materials and RRAM cell structures affect performance. In chapter 3 we built models based on Stanford-PKU RRAM model and 0.18um TSMC N-MOSFET. The simulation results of the RRAM cell model, the 1T1R RRAM structure model and 1T1R RRAM array model are analyzed in chapter 4. Based on the simulation results, methods are proposed to solve the problem occurring during the SPICE code running with the LTspice simulator.en_US
dc.language.isoenen_US
dc.publisherNanyang Technological Universityen_US
dc.subjectEngineering::Electrical and electronic engineering::Electronic circuitsen_US
dc.titleLTspice implementation of PKU compact model of metal-oxide-based RRAM: part C_simulation of RRAM memory arraysen_US
dc.typeThesis-Master by Courseworken_US
dc.contributor.supervisorChen Tupeien_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Science (Electronics)en_US
dc.contributor.supervisoremailEChenTP@ntu.edu.sgen_US
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