Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/159497
Title: Longevity framework: leveraging online integrated aging-aware hierarchical mapping and VF-selection for lifetime reliability optimization in manycore processors
Authors: Rathore, Vijeta
Chaturvedi, Vivek
Singh, Amit K.
Srikanthan, Thambipillai
Shafique, Muhammad
Keywords: Engineering::Computer science and engineering
Issue Date: 2020
Source: Rathore, V., Chaturvedi, V., Singh, A. K., Srikanthan, T. & Shafique, M. (2020). Longevity framework: leveraging online integrated aging-aware hierarchical mapping and VF-selection for lifetime reliability optimization in manycore processors. IEEE Transactions On Computers, 70(7), 1106-1119. https://dx.doi.org/10.1109/TC.2020.3006571
Journal: IEEE Transactions on Computers
Abstract: Rapid device aging in the nano era threatens system lifetime reliability, posing a major intrinsic threat to system functionality. Traditional techniques to overcome the aging-induced device slowdown, such as guardbanding are static and incur performance, power, and area penalties. In a manycore processor, the system-level design abstraction offers dynamic opportunities through the control of task-to-core mappings and per-core operation frequency towards more balanced core aging profile across the chip, optimizing the system lifetime reliability while meeting the application performance requirements. This article presents Longevity Framework (LF) that leverages online integrated aging-aware hierarchical mapping and voltage frequency (VF)-selection for lifetime reliability optimization in manycore processors. The mapping exploration is hierarchical to achieve scalability. The VF-selection builds on the trade-offs involved between power, performance, and aging as the VF is scaled while leveraging the per-core DVFS capabilities. The methodology takes the chip-wide process variation into account. Extensive experimentation, comparing the proposed approach with two state-of-the-art methods, for 64-core and 256-core systems running applications from PARSEC and SPLASH-2 benchmark suites, show an improvement of up to 3.2 years in the system lifetime reliability and 4×improvement in the average core health.
URI: https://hdl.handle.net/10356/159497
ISSN: 0018-9340
DOI: 10.1109/TC.2020.3006571
Schools: School of Computer Science and Engineering 
Rights: © 2020 IEEE. All rights reserved.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:SCSE Journal Articles

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