Simulation of dopant distribution inside group IV nanowires

Abstract

This report describes a series of process and device simulation experiments of Group IV silicon nanowires based on Taurus TSUPREM-4. Fabrication process, dopant distribution profile and changing in electrical properties are observed and discussed. The silicon nanowire is a kind of new generation device, which has smaller dimension and faster speed comparing with conventional CMOS devices. Silicon nanowires can be fabricated using Top-Down and Bottom-Up methods with respective advantages and disadvantages. Due to the small dimension, the high surface to volume ratio indicates the surface structure and states are critical factors determining the performance of nanowires. Boron, phosphorus and arsenic impurities were doped into nanowire by ion implantation. The dopant distribution profiles inside nanowires were investigated to choose suitable implantation conditions and ensure the projection range Rp is inside the nanowire. Rapid thermal annealing (RTA) was applied to restore the crystalline damage during the implantation and activate the impurity atoms. The dopant distribution profile after RTA was observed with possible explanations. I-V measurement can directly determine the effects of dopant inside nanowires upon the electrical properties. Due to the surface structure, dangling bonds could seriously affect the conductivity and should be removed before doing RTA. Therefore, the forming gas annealing (FGA) was introduced. The effects of FGA were discussed. The results showed the FGA process could enhance the conductivity by 2-8 times. Four FGA methods were compared to evaluate the factors affecting FGA. The results showed direct reaction between H2 forming gas and silicon nanowire could achieve the highest conductivity.