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dc.contributor.authorZhao, Guangchaoen_US
dc.contributor.authorWang, Xinglien_US
dc.contributor.authorYip, Weng Houen_US
dc.contributor.authorVinh Huy, Nguyen Toen_US
dc.contributor.authorCoquet, Philippeen_US
dc.contributor.authorHuang, Mingqiangen_US
dc.contributor.authorTay, Beng Kangen_US
dc.identifier.citationZhao, G., Wang, X., Yip, W. H., Vinh Huy, N. T., Coquet, P., Huang, M. & Tay, B. K. (2022). Ternary logics based on 2D ferroelectric-incorporated 2D semiconductor field effect transistors. Frontiers in Materials, 9, 872909-.
dc.description.abstractTernary logic has been proven to carry an information ratio 1.58 times that of binary logic and is capable to reduce circuit interconnections and complexity of operations. However, the excessive transistor count of ternary logic gates has impeded their industry applications for decades. With the modulation of the ferroelectric negative capacitance (NC) properties on the channel potential, MOSFETs show many novel features including steep subthreshold swing and non-saturation output characteristics, based on which an ultra-compact ternary inverter can be achieved. Compared with traditional bulk materials, layered 2D materials and 2D ferroelectrics provide a clean interface and better electrostatic control and reliability. Even though ultra-low SS (∼10 mV/dec) has been experimentally demonstrated in ferroelectric-negative capacitance-incorporated 2D semiconductor (NC2D) FETs, the available models are still rare for large-scale circuit simulations. In this study, the superb electrical properties of pure 2D material stack-based NC2D FETs (layered CuInP2S6 adopted as the 2D ferroelectric layer) are investigated through device modeling based on the Landau–Khalatnikov (LK) equations in HSPICE. We managed to realize an ultra-compact ternary inverter with one NC2D-PMOS (WSe2) and one NC2D-NMOS (MoS2) in HSPICE simulations, whose transistor count is significantly reduced compared with other counterparts. We also proposed a novel input waveform scheme to solve the hysteresis problem caused by ferroelectric modulation to avoid logic confusion. Additionally, the power consumption and propagation delay of the NC2D-based ternary inverter are also investigated. This work may provide some insights into the design and applications of ferroelectric-incorporated 2D semiconductor devices.en_US
dc.description.sponsorshipMinistry of Education (MOE)en_US
dc.relation.ispartofFrontiers in Materialsen_US
dc.rights© 2022 Zhao, Wang, Yip, Vinh Huy, Coquet, Huang and Tay. This is an open-access article distributed under the terms of the Creative Commons Attribution License (CC BY). The use, distribution or reproduction in other forums is permitted, provided the original author(s) and the copyright owner(s) are credited and that the original publication in this journal is cited, in accordance with accepted academic practice. No use, distribution or reproduction is permitted which does not comply with these terms.en_US
dc.subjectEngineering::Electrical and electronic engineeringen_US
dc.titleTernary logics based on 2D ferroelectric-incorporated 2D semiconductor field effect transistorsen_US
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.contributor.researchCentre for Micro-/Nano-electronics (NOVITAS)en_US
dc.contributor.researchCNRS International NTU THALES Research Alliancesen_US
dc.description.versionPublished versionen_US
dc.subject.keywordsTernary Logicsen_US
dc.subject.keywords2D Semiconductorsen_US
dc.description.acknowledgementThis research work was supported by the Ministry of Education, Singapore, under its MOE Tier 2 project (MOE2019-T2-2-075), Shenzhen Science and Technology Innovation Committee JCYJ20200109115210307, and Guangdong Basic and Applied Basic Research Foundation 2019A1515111142, China.en_US
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