Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/160503
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dc.contributor.authorKar, Bapien_US
dc.contributor.authorGopalakrishnan, Pradeep Kumaren_US
dc.contributor.authorBose, Sumon Kumaren_US
dc.contributor.authorRoy, Mohendraen_US
dc.contributor.authorBasu, Arindamen_US
dc.date.accessioned2022-07-25T08:26:45Z-
dc.date.available2022-07-25T08:26:45Z-
dc.date.issued2020-
dc.identifier.citationKar, B., Gopalakrishnan, P. K., Bose, S. K., Roy, M. & Basu, A. (2020). ADIC: anomaly detection integrated circuit in 65-nm CMOS utilizing approximate computing. IEEE Transactions On Very Large Scale Integration (VLSI) Systems, 28(12), 2518-2529. https://dx.doi.org/10.1109/TVLSI.2020.3016939en_US
dc.identifier.issn1063-8210en_US
dc.identifier.urihttps://hdl.handle.net/10356/160503-
dc.description.abstractIn this paper, we present a low-power anomaly detection integrated circuit (ADIC) based on a one-class classifier (OCC) neural network. The ADIC achieves low-power operation through a combination of (a) careful choice of algorithm for online learning and (b) approximate computing techniques to lower average energy. In particular, online pseudoinverse update method (OPIUM) is used to train a randomized neural network for quick and resource efficient learning. An additional 42% energy saving can be achieved when a lighter version of OPIUM method is used for training with the same number of data samples lead to no significant compromise on the quality of inference. Instead of a single classifier with large number of neurons, an ensemble of K base learner approach is chosen to reduce learning memory by a factor of K. This also enables approximate computing by dynamically varying the neural network size based on anomaly detection. Fabricated in 65nm CMOS, the ADIC has K = 7 Base Learners (BL) with 32 neurons in each BL and dissipates 11.87pJ/OP and 3.35pJ/OP during learning and inference respectively at Vdd = 0.75V when all 7 BLs are enabled. Further, evaluated on the NASA bearing dataset, approximately 80% of the chip can be shut down for 99% of the lifetime leading to an energy efficiency of 0.48pJ/OP, an 18.5 times reduction over full-precision computing running at Vdd = 1.2V throughout the lifetime.en_US
dc.description.sponsorshipNational Research Foundation (NRF)en_US
dc.language.isoenen_US
dc.relation.ispartofIEEE Transactions on Very Large Scale Integration (VLSI) Systemsen_US
dc.rights© 2020 IEEE. All rights reserved.en_US
dc.subjectEngineering::Electrical and electronic engineeringen_US
dc.titleADIC: anomaly detection integrated circuit in 65-nm CMOS utilizing approximate computingen_US
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.contributor.researchDelta-NTU Corporate Laboratory for Cyber Physical Systemsen_US
dc.identifier.doi10.1109/TVLSI.2020.3016939-
dc.identifier.scopus2-s2.0-85097353599-
dc.identifier.issue12en_US
dc.identifier.volume28en_US
dc.identifier.spage2518en_US
dc.identifier.epage2529en_US
dc.subject.keywordsAnomaly Detectionen_US
dc.subject.keywordsApproximate Computingen_US
dc.description.acknowledgementThis work was supported in part by Delta Electronics Inc. and in part by the National Research Foundation Singapore under the Corporate Laboratory@UniversityScheme.en_US
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item.grantfulltextnone-
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