Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/161227
Title: High-speed and energy-efficient carry look-ahead adder
Authors: Balasubramanian, Padmanabhan 
Mastorakis, Nikos E.
Keywords: Engineering::Computer science and engineering::Hardware::Arithmetic and logic structures
Engineering::Electrical and electronic engineering::Integrated circuits
Engineering::Electrical and electronic engineering::Microelectronics
Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2022
Source: Balasubramanian, P. & Mastorakis, N. E. (2022). High-speed and energy-efficient carry look-ahead adder. Journal of Low Power Electronics and Applications, 12(3), 46-. https://dx.doi.org/10.3390/jlpea12030046
Journal: Journal of Low Power Electronics and Applications
Abstract: The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison.
URI: https://hdl.handle.net/10356/161227
ISSN: 2079-9268
DOI: 10.3390/jlpea12030046
Schools: School of Computer Science and Engineering 
Research Centres: Hardware & Embedded Systems Lab (HESL) 
Rights: © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Journal Articles

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