Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/161806
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dc.contributor.authorFeng, Tianyien_US
dc.date.accessioned2022-09-20T07:41:54Z-
dc.date.available2022-09-20T07:41:54Z-
dc.date.issued2022-
dc.identifier.citationFeng, T. (2022). Data transmission in clock domain crossing and data reconfiguration based on asynchronous FIFO. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/161806en_US
dc.identifier.urihttps://hdl.handle.net/10356/161806-
dc.description.abstractWith the continuous development of electronic devices and VLSI manufacturing processes, the logic between high-speed processors has become increasingly complex, and more transistors have been integrated on the chip. And SoC has become the mainstream trend in chip manufacturing. Data transmission in clock domain crossing is common in SoC designing process, which also brings a lot of problems including metastability and data loss to designers. In this project, an asynchronous FIFO is designed to solve such problems. And then, an intellectual property core based on FIFO is designed to transfer a bulk of data in cross-clock domain and reconfigure the data.en_US
dc.language.isoenen_US
dc.publisherNanyang Technological Universityen_US
dc.subjectEngineering::Electrical and electronic engineeringen_US
dc.titleData transmission in clock domain crossing and data reconfiguration based on asynchronous FIFOen_US
dc.typeThesis-Master by Courseworken_US
dc.contributor.supervisorZheng Yuanjinen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Science (Electronics)en_US
dc.contributor.supervisoremailYJZHENG@ntu.edu.sgen_US
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