Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/161806
Title: Data transmission in clock domain crossing and data reconfiguration based on asynchronous FIFO
Authors: Feng, Tianyi
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2022
Publisher: Nanyang Technological University
Source: Feng, T. (2022). Data transmission in clock domain crossing and data reconfiguration based on asynchronous FIFO. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/161806
Abstract: With the continuous development of electronic devices and VLSI manufacturing processes, the logic between high-speed processors has become increasingly complex, and more transistors have been integrated on the chip. And SoC has become the mainstream trend in chip manufacturing. Data transmission in clock domain crossing is common in SoC designing process, which also brings a lot of problems including metastability and data loss to designers. In this project, an asynchronous FIFO is designed to solve such problems. And then, an intellectual property core based on FIFO is designed to transfer a bulk of data in cross-clock domain and reconfigure the data.
URI: https://hdl.handle.net/10356/161806
Schools: School of Electrical and Electronic Engineering 
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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