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|Title:||Digital image blending by inexact multiplication||Authors:||Balasubramanian, Padmanabhan
Maskell, Douglas L.
|Keywords:||Engineering::Electrical and electronic engineering::Integrated circuits
Engineering::Electrical and electronic engineering::Electronic circuits
Engineering::Computer science and engineering::Hardware
|Issue Date:||2022||Source:||Balasubramanian, P., Nayar, R., Min, O. & Maskell, D. L. (2022). Digital image blending by inexact multiplication. Electronics, 11(18), 2868-. https://dx.doi.org/10.3390/electronics11182868||Project:||MOE2018-T2-2-024||Journal:||Electronics||Abstract:||Digital image blending is commonly used in applications such as photo editing and computer graphics where two images are combined to produce a desired blended image. Digital images can be blended by addition or multiplication, and usually exact addition or multiplication is performed for image blending. In this paper, we evaluate the usefulness of inexact multiplication for digital image blending. Towards this, we describe how an exact array multiplier can be made inexact by introducing vertical cut(s) in it and assigning distinct combinations of binary values to the dangling inputs and product bits. We considered many 8-bit digital images for blending and the blended images obtained using exact and inexact multipliers are shown, which demonstrates the usefulness of inexact multiplication for image blending. For 8 × 8 image blending, one of our inexact array multipliers viz. IAM01-VC8 was found to achieve 63.3% reduction in area, 21% reduction in critical path delay, 72.3% reduction in power dissipation, and 78.1% reduction in energy compared to the exact array multiplier. In addition, IAM01-VC8 achieved 60.6% reduction in area, 9.7% reduction in critical path delay, 64.7% reduction in power dissipation, and 68.1% reduction in energy compared to the high-speed exact 8 × 8 multiplier that was automatically synthesized using a logic synthesis tool. The exact and inexact multipliers were physically realized using 32/28 nm CMOS process technology.||URI:||https://hdl.handle.net/10356/161818||ISSN:||2079-9292||DOI:||10.3390/electronics11182868||Schools:||School of Computer Science and Engineering||Research Centres:||Hardware & Embedded Systems Lab (HESL)
Transport Research Centre
|Rights:||© 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||SCSE Journal Articles|
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