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|Title:||Studies on the performance bounds and design of current-steering DACs||Authors:||Chacón, Oscar Morales||Keywords:||Engineering::Electrical and electronic engineering||Issue Date:||2022||Publisher:||Nanyang Technological University||Source:||Chacón, O. M. (2022). Studies on the performance bounds and design of current-steering DACs. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/162533||Project:||Joint-PhD Program NTU-LiU||Abstract:||Digital-to-analog converters (DACs) are key building blocks in various applications including radar and wireless communications. With the exponential growth of data throughput in modern communication standards, e.g., fifth-generation (5G), DACs has been pushed to achieve direct frequency synthesis in the GHz-range with channel bandwidths preferably beyond 1 GHz. Yet, higher frequency synthesis results in augmented power consumption, which can significantly impact the wireless network if multiple DACs are utilized, e.g., in massive multiple-input and multiple-output (MIMO) antenna systems with digital beamforming as well as in end-user’s handheld devices subject to a less prolonged battery life. Moreover, advances in digital signal processing and integrated-circuit fabrication, leading to reduced power consumption and cost as well as more flexibility in software-defined radio transmitters have motivated the displacement of analog/RF circuits to the digital domain. At the same time, driving the DACs to cover the millimeter-Wave (mm-Wave) spectrum, ranging between 30-300 GHz. In this work, high-speed DACs operating in the GHz-range with maintained low power consumption is addressed. The Nyquist-rate DAC is chosen due to its simple conversion approach to facilitate the generation of channel bandwidths in the GHz-range. A 10-bit current-steering (CS) Nyquist DAC realized in 65-nm CMOS is presented. The design is intended for low-complexity and power consumption while targeting high-speed operation with over 1 GHz channel bandwidth and maintained linearity. The binary-weighted architecture is considered to achieve straightforward digital-to analog conversion. Next, a theoretical analysis to obtain the energy consumption bounds in CS DACs is presented. The analysis considers the digital, mixed-signal and analog power domains as well as the design corners of noise, speed and linearity. This is validated from reported measurement results in published CS DACs implemented in CMOS technology. Furthermore, design considerations with enhancement techniques are addressed. A digital switching scheme to avoid complementary switching transitions and counteract for timing errors is presented. The proposed scheme improves also the yield in linearity due to stochastic amplitude errors with reduced switching activity. Then, a comparative analysis of latch-drivers commonly implemented in CS DACs is realized. The comparison includes single- and dual-clocked latch-drivers and an alternative solution is proposed to reduce the switching-delay and power consumption.||URI:||https://hdl.handle.net/10356/162533||URL:||http://www.diva-portal.org/smash/record.jsf?pid=diva2%3A1697422&dswid=-2243||DOI:||10.32657/10356/162533||Rights:||This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License (CC BY-NC 4.0).||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
Updated on Nov 25, 2022
Updated on Nov 25, 2022
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