Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/162707
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dc.contributor.authorChacón, Oscar Moralesen_US
dc.contributor.authorWikner, J. Jacoben_US
dc.contributor.authorSvensson, Christeren_US
dc.contributor.authorSiek, Literen_US
dc.contributor.authorAlvandpour, Atilaen_US
dc.date.accessioned2022-11-07T04:49:16Z-
dc.date.available2022-11-07T04:49:16Z-
dc.date.issued2022-
dc.identifier.citationChacón, O. M., Wikner, J. J., Svensson, C., Siek, L. & Alvandpour, A. (2022). Analysis of energy consumption bounds in CMOS current-steering digital-to-analog converters. Analog Integrated Circuits and Signal Processing, 111(3), 339-351. https://dx.doi.org/10.1007/s10470-022-02013-2en_US
dc.identifier.issn0925-1030en_US
dc.identifier.urihttps://hdl.handle.net/10356/162707-
dc.description.abstractIn this paper, an attempt to estimate energy consumption bounds versus signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) in CMOS current-steering digital-to-analog converters is presented. A theoretical analysis is derived, including the design corners for noise, speed and linearity for the mixed-signal domain. The study is validated by comparing the theoretical results with published measured data. As result it serves as a design reference to aim for minimum energy consumption. It is found that for an equivalent number of bits (ENOBs), the noise-bound grows at a rate of 22ENOB, whereas the speed-bound increases by 2ENOB−2 and is dependent on device dimensions. Therefore, as the technology scales down, the noise bound will dominate, which is observed for an estimated SNR of about 40 dB in 65 nm CMOS process. The linearity bound is derived from an analysis based on the assumption of limited output impedance, where it is found to be dependent on the device dimensions and increase at a rate of 2ENOB−1. The observations show that it is possible to achieve less energy consumption in all the design corners for different SNR and SFDR specifications within the Nyquist frequency, fs/2.en_US
dc.language.isoenen_US
dc.relation.ispartofAnalog Integrated Circuits and Signal Processingen_US
dc.rights© The Author(s) 2022. Open Access. This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if changes were made. The images or other third party material in this article are included in the article’s Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit http://creativecommons. org/licenses/by/4.0/.en_US
dc.subjectEngineering::Electrical and electronic engineeringen_US
dc.titleAnalysis of energy consumption bounds in CMOS current-steering digital-to-analog convertersen_US
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doi10.1007/s10470-022-02013-2-
dc.description.versionPublished versionen_US
dc.identifier.scopus2-s2.0-85127279834-
dc.identifier.issue3en_US
dc.identifier.volume111en_US
dc.identifier.spage339en_US
dc.identifier.epage351en_US
dc.subject.keywordsDigital-to-Analog Converteren_US
dc.subject.keywordsCMOSen_US
dc.description.acknowledgementThis work is financially supported by innovation agency (VINNOVA) under project 2017-04891, the strategic research environment funded by the Swedish government (ELLIIT), and the Swedish foundation for international cooperation in research and higher education (STINT). Open access funding provided by Linkoping University.en_US
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