Energy-efficient analog-to-digital conversion for in-memory computing

Abstract

In-Memory Computing is a trending approach tackling power overhead and latency from the conventional von Neumann architecture. ADC is a commonly utilized power-hungry component that converts analog intermediate computing results to digital form for further operations. However, it is challenging to achieve energy-efficient ADCs for IMC with high accuracy. Moreover, low-supply devices usually suffer from PVT variations which degrades performance. In this study, an 8-bit SAR ADC is implemented, which utilizes a monotonic set-and-down switching method with a PVT-variation compensation system. Adaptations to IMC-specific requirements are adopted, such as using transmission gates as input switches, inverted StrongARM comparator with pMOS as input transistors, improved digital control circuit for lower power and higher accuracy, and adapted locking criteria for local supply generation. Simulated using 65nm CMOS technology at 27°C under 1V supply voltage and sampling at 50 MS/s, the circuit achieves ENOB of 7.75 bits, FOM of 38.87 fJ/Conv.-step, RMSE of 0.3515 standalone. When connected in IMC and under favorable conditions of 80°C or +5% supply voltage, the power is comparable to the same ADC structure without compensation. Under unfavorable conditions such as -20°C or -5% supply, the accuracy is maintained while power increases.