Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/163745
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dc.contributor.authorSu, Yuqien_US
dc.contributor.authorMu, Junjieen_US
dc.contributor.authorKim, Hyunjoonen_US
dc.contributor.authorKim, Bongjinen_US
dc.date.accessioned2022-12-15T08:22:21Z-
dc.date.available2022-12-15T08:22:21Z-
dc.date.issued2022-
dc.identifier.citationSu, Y., Mu, J., Kim, H. & Kim, B. (2022). A scalable CMOS Ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problems. IEEE Journal of Solid-State Circuits, 57(3), 858-868. https://dx.doi.org/10.1109/JSSC.2022.3142896en_US
dc.identifier.issn0018-9200en_US
dc.identifier.urihttps://hdl.handle.net/10356/163745-
dc.description.abstractNo existing algorithms can find exact solutions to the combinatorial optimization problems (COPs) classified as non-deterministic polynomial-time (NP) hard problems. Alternatively, Ising computer based on the Ising model and annealing process has recently drawn significant attention. The Ising computers can find approximate solutions to the NP-hard COPs by observing the convergence of dynamic spin states. However, they have encountered challenges in mapping the optimization problems to the inflexible Ising computers with fixed spin interconnects. In this article, we propose a scalable CMOS Ising computer with sparse and reconfigurable spin interconnects for arbitrary mapping of spin networks with minimal overhead. Without a mapping algorithm, the proposed Ising computer provides a method for directly mapping COPs to the reconfigurable hardware. A 65-nm CMOS Ising test chip with 252 spins is fabricated and used for solving COPs, including max-cut problems.en_US
dc.language.isoenen_US
dc.relation.ispartofIEEE Journal of Solid-State Circuitsen_US
dc.rights© 2022 IEEE. All rights reserved.en_US
dc.subjectEngineering::Electrical and electronic engineeringen_US
dc.titleA scalable CMOS Ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problemsen_US
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doi10.1109/JSSC.2022.3142896-
dc.identifier.scopus2-s2.0-85123739676-
dc.identifier.issue3en_US
dc.identifier.volume57en_US
dc.identifier.spage858en_US
dc.identifier.epage868en_US
dc.subject.keywordsIntegrated Circuit Interconnectionsen_US
dc.subject.keywordsComputational Modelingen_US
item.grantfulltextnone-
item.fulltextNo Fulltext-
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