Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/163745
Title: A scalable CMOS Ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problems
Authors: Su, Yuqi
Mu, Junjie
Kim, Hyunjoon
Kim, Bongjin
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2022
Source: Su, Y., Mu, J., Kim, H. & Kim, B. (2022). A scalable CMOS Ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problems. IEEE Journal of Solid-State Circuits, 57(3), 858-868. https://dx.doi.org/10.1109/JSSC.2022.3142896
Journal: IEEE Journal of Solid-State Circuits 
Abstract: No existing algorithms can find exact solutions to the combinatorial optimization problems (COPs) classified as non-deterministic polynomial-time (NP) hard problems. Alternatively, Ising computer based on the Ising model and annealing process has recently drawn significant attention. The Ising computers can find approximate solutions to the NP-hard COPs by observing the convergence of dynamic spin states. However, they have encountered challenges in mapping the optimization problems to the inflexible Ising computers with fixed spin interconnects. In this article, we propose a scalable CMOS Ising computer with sparse and reconfigurable spin interconnects for arbitrary mapping of spin networks with minimal overhead. Without a mapping algorithm, the proposed Ising computer provides a method for directly mapping COPs to the reconfigurable hardware. A 65-nm CMOS Ising test chip with 252 spins is fabricated and used for solving COPs, including max-cut problems.
URI: https://hdl.handle.net/10356/163745
ISSN: 0018-9200
DOI: 10.1109/JSSC.2022.3142896
Schools: School of Electrical and Electronic Engineering 
Rights: © 2022 IEEE. All rights reserved.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Journal Articles

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