Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/164963
Title: Discrete-time delta-sigma analog-to-digital converter using VCO-based quantizer for IoT applications
Authors: An, Kyung-Chan
Keywords: Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2022
Publisher: Nanyang Technological University
Source: An, K. (2022). Discrete-time delta-sigma analog-to-digital converter using VCO-based quantizer for IoT applications. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/164963
Abstract: Low-power systems are essential for Internet-of-Things (IoT) applications powered by harvested energy or batteries, such as wearable devices, structural health monitoring, industrial process monitoring, and personal health monitoring. Analog to digital converter (ADC) is an essential part of the IoT sensor interface and communication system that receives analog signals such as radio waves, light, sound, and biological signals. Depending on the purpose, the ADC is designed for the targets of low voltage operation, dynamic voltage scaling, and high resolution. The technology and supply voltage scaling caused by technological advances reduce voltage headroom and signal power, which makes it challenging to achieve high performance in analog circuit design. A voltage-controlled oscillator (VCO) based ADC that processes analog information in the time domain can be desirable for technology and supply voltage scaling. However, the conventional VCO-based ADCs present challenges such as dynamic voltage scaling, process variation, narrow input range, and discrete-time operation. For high-resolution ADC design, ΔΣ ADC began regaining its popularity as a research topic for high resolution. The discrete-time (DT) ΔΣ ADC effectively reduces two primary noise sources. They are quantization noise and kT/C noise. kT/C noise is more prominent than the quantization noise in high-resolution ADC. kT/C noise is inversely proportional to sampling capacitance and oversampling ratio (OSR). Therefore, high OSR and large capacitance reduce the kT/C noise. Generally, high OSR is preferred to the large capacitance, for the area and power efficiency. However, high-resolution ADC designs are limited in environments where a high OSR cannot be applied. This thesis provides existing ADCs' history and insight into the advantages and disadvantages through literature review and behavioral simulation of existing ADCs for low-power and high-resolution. In addition, a design of discrete-time OTA-free VCO-based 2nd order ΣΔ ADC familiar with dynamic voltage frequency scaling (DVFS) and a study on achieving high resolution in an OSR-limited environment are introduced. Scaling-friendly discrete-time OTA-Free ΔΣ-ADC consists of a linear VCO, passive filter, and a fully digital frequency delta-sigma modulator (FDSM). The linear VCO operates as discrete-time and has controllable linear voltage-to-frequency characteristics. This does not require an additional nonlinearity calibration block. The controllable linear V-to-F characteristics enable the ADC design for DVFS and eliminate the need for additional nonlinearity calibration blocks. This highly digital architecture facilitates a trade-off between the supply voltage and the operational bandwidth and makes the design suitable for energy-efficient IoT applications. A study on achieving high resolution in an OSR-limited design condition proposes the ΣΔ ADC architecture which suffers less from KT/C noise with low OSR. The concept is to reduce the effect of kT/C noise generated by the loop filter, by placing the gain stage in front of the loop filter. The gain-stage consists of the capacitor feedback inverting amplifier (CFIA) and an active lossy integrator, while the overall gain is the product of the two. The proposed architecture effectively reduces the kT/C noise power from the loop filter as much as the squared gain of the added gain-stage. The gain-stage greatly relaxes the loop filter's sampling capacitor requirements. This architecture facilitates a high-resolution ADC design in an OSR-limited design condition.
URI: https://hdl.handle.net/10356/164963
DOI: 10.32657/10356/164963
Schools: School of Electrical and Electronic Engineering 
Research Centres: VIRTUS, IC Design Centre of Excellence 
Rights: This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License (CC BY-NC 4.0).
Fulltext Permission: embargo_20240930
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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