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Title: EdgeNAS: discovering efficient neural architectures for edge systems
Authors: Luo, Xiangzhong
Liu, Di
Kong, Hao
Liu, Weichen
Keywords: Engineering::Computer science and engineering
Issue Date: 2020
Source: Luo, X., Liu, D., Kong, H. & Liu, W. (2020). EdgeNAS: discovering efficient neural architectures for edge systems. 2020 IEEE 38th International Conference on Computer Design (ICCD), 288-295.
Project: MOE2019-T2-1-071 
MOE2019-T1- 001-072 
NAP (M4082282) 
SUG (M4082087) 
Conference: 2020 IEEE 38th International Conference on Computer Design (ICCD)
Abstract: Edge systems integrated with deep neural networks (DNNs) are deemed to pave the way for future artificial intelligence (AI). However, designing accurate and efficient DNNs for resource-limited edge systems is challenging as well as requires a huge amount of engineering efforts from human experts since the design space is highly complex and diverse. Also, previous works mostly focus on designing DNNs with less floating-point operations (FLOPs), but indirect FLOPs count does not necessarily reflect the complexity of DNNs. To tackle these, we, in this paper, propose a novel neural architecture search (NAS) approach, namely EdgeNAS, to automatically discover efficient DNNs for less capable edge systems. To this end, we propose an end-to-end learning-based latency estimator, which is able to directly approximate the architecture latency on edge systems while incurring negligible computational overheads. Further, we effectively incorporate the latency estimator into EdgeNAS with a uniform sampling strategy, which guides the architecture search towards an edge-efficient direction. Moreover, a search space regularization approach is introduced to balance the trade-off between efficiency and accuracy. We evaluate EdgeNAS on the edge platform, Nvidia Jetson Xavier, with three popular datasets. Experimental results demonstrate the superiority of EdgeNAS over state-of-the-art approaches in terms of latency, accuracy, number of parameters, and the search cost.
DOI: 10.1109/ICCD50377.2020.00056
DOI (Related Dataset): 10.21979/N9/L2QVIV
Schools: School of Computer Science and Engineering 
Research Centres: Parallel and Distributed Computing Centre 
Rights: © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at:
Fulltext Permission: open
Fulltext Availability: With Fulltext
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