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Title: Dual-gate all-electrical valleytronic transistors
Authors: Lai, Shen
Zhang, Zhaowei
Wang, Naizhou
Abdullah Rasmita
Deng, Ya
Liu, Zheng
Gao, Weibo
Keywords: Science::Physics
Issue Date: 2023
Source: Lai, S., Zhang, Z., Wang, N., Abdullah Rasmita, Deng, Y., Liu, Z. & Gao, W. (2023). Dual-gate all-electrical valleytronic transistors. Nano Letters, 23(1), 192-197.
Project: NRF-CRP22-2019-0004 
MOE2016-T3-1-006 (S) 
Journal: Nano Letters 
Abstract: The development of integrated circuits (ICs) based on a complementary metal−oxide−semiconductor through transistor scaling has reached the technology bottleneck; thus, alternative approaches from new physical mechanisms are highly demanded. Valleytronics in two-dimensional (2D) material systems has recently emerged as a strong candidate, which utilizes the valley degree of freedom to process information for electronic applications. However, for all-electrical valleytronic transistors, very low room- temperature “valley on−off” ratios (around 10) have been reported so far, which seriously limits their practical applications. In this work, we successfully illustrated both n- and p-type valleytronic transistor performances in monolayer MoS2 and WSe2 devices, with measured “valley on−off” ratios improved up to 3 orders of magnitude greater compared to previous reports. Our work shows a promising way for the electrically controllable manipulation of valley degree of freedom toward practical device applications.
ISSN: 1530-6984
DOI: 10.1021/acs.nanolett.2c03947
Schools: School of Physical and Mathematical Sciences 
School of Materials Science and Engineering 
Rights: This document is the Accepted Manuscript version of a Published Work that appeared in final form in Nano Letters, copyright © 2023 American Chemical Society, after peer review and technical editing by the publisher. To access the final edited and published work see
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:MSE Journal Articles
SPMS Journal Articles

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