Design of time-to-digital converter and chip applications

Abstract

Time-to-digital converter (TDC) is very important in products which need precise time meaurement, compact size and low power consumption. In this thesis, a 8-stages GRO (Gated Ring Oscillator) TDC with high resolution and high linearity is presented. A fully delay cell gated ring oscillator and TSPC are mainly placed in this architecture. The counting measure consists of two parts, coarse time counting and fine time counting respectively. Coarse counter is applied in order to increase the dynamic range, while fine counter is focused on resolution. In a 55nm BCD GF technology, the proposed TDC reaches a large detectable range and high precision. The core TDC’s total power consumption is only 10.5mW with 1.2V power supply.