Minimum energy driven ultra-low voltage SRAM

Abstract

The development of memory technology towards more compact and higher storage densities is increasingly challenging due to requirements such as small device sizes, power consumption, and low-voltage operations. However, smaller device sizes yield increasing process variations and, in conjunction with ultra-low voltage operations, decrease the stability of the memory. This project analyzes the 6T, 8T, and 10T SRAM topologies and discusses the relation between the Static Noise Margins, transistor ratio, and supply voltages of each topology. Furthermore, the relations between energy consumption, supply voltage, process corners, and temperature are also discussed. Afterward, considering the trade-offs between SRAM topology, size, static noise margin, access time, and energy consumption in the design process, a 1kb SRAM array capable of a simultaneous 16-bit read and write operation is implemented using the 8T SRAM topology, which is able to operate on a supply voltage down to 600mV, achieving a leakage current 31.8nA, read energy of 35.8fJ, and write energy of 68.8fJ, which are 35%, 17%, and 20% of their respective values at a supply voltage of 1.2V.