Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/16704
Title: Low-power flip-flop circuits for high-performance systems
Authors: Tang, Pey Chyi.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2009
Abstract: The main purpose of this project was to design low power and high performance flip-flop. This was because flip-flops are one of the most important components in today’s very large-scale integration (VLSI) design. The design of a flip-flop with low power consumption and high speed had become a major concern as there is a continuous increase of clock frequency, chip density and pipeline stages. In this report, studies on the recently published CMOS flip-flops were conducted with focus on sense-amplifier based flip-flops (SAFF). Two single-edge triggered sense-amplifier flip-flops were proposed for low power and high performance applications. The proposed flip-flops were designed using Chartered Semiconductor 0.18 µm CMOS process and compared to other previously published flip-flops. The first design, namely the clock gating sense-amplifier flip-flop (CGSAFF) was designed using the clock gating technique. The conditional clock inverting circuit was used to eliminate the redundant transition at both the clock path and the internal nodes. The simulation results showed that CGSAFF could achieve significant power reduction at data switching activities of less than 0.5. At the maximum switching activities, its power delay product (PDP) was noted to improve by about 2.4% to 50.2% when compare to other state-of-the art flip-flops simulated in this project. The second design, namely the static pulsed sense-amplifier flip-flop (SPSAFF) was designed to further minimize the power consumption at high input switching activities. The proposed SPSAFF was developed by modifying the proposed CGSAFF. The conditional circuitry was removed from this circuit and modification was done to the sensing stage to improve on the power consumption and the CLK-to-Q delay. The simulated results indicated that the proposed SPSAFF has the lowest power consumption of 933 mW and PDP of 85.06 fJ among the simulated flip-flop circuits when operating at maximum input switching activities. Moreover, the proposed flip-flop had a negative setup time that allows time borrowing.
URI: http://hdl.handle.net/10356/16704
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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