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|Title:||Analysis and design of high speed low power 4-bit ALU||Authors:||Huang, Si Wei.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits||Issue Date:||2009||Abstract:||This project is introduced to the student to get hands-on experience in fundamentals of Very Large Scale Integrated circuit design. Arithmetic Logic Unit (ALU), an important building block in microprocessor, is chosen as the research topic. The student is required to build a 4-Bit ALU with basic computation and logic functionality. The design criteria are High speed, Low power consumption and Small area. High speed objective is achieved by implementing Carry Look-ahead adder cell and utilizing Chain structure for ALU. The low power objective is achieved at circuit level by eliminating direct paths between the supply voltage and ground, and by maintaining low switching activity in the circuit. This project has gone through three stages. At first stage, the student studied different building blocks in the microprocessor system, understood the various low power design techniques used in microprocessor and finally fixed the research interest on ALU design with the goal of high speed and low power. At second stage, from transistor level the student built up logic gates like INV, AND, OR, TG, XOR, MUX. They were optimized to achieve low power. Afterwards, textbook based full adder cell, and standard Transmission Gate adder cell were constructed. Afterwards Controlled Adder/Subtractor (CAS) cell were constructed to realize addition and subtraction within one cell. At the third stage, by putting the logic gates and CAS blocks together two types of 4-Bit ALUs were constructed. And then these two ALUs were tested and evaluated. Discussion and future research were presented too. The base design of ALU was done using static CMOS logic. The designed ALU performs 8 operations. It can add, subtract, logic AND, OR, XOR, invert and pass data. It has two 4-bit data inputs, one 3 bit select line, and a 5-bit (4-bits and a carry/borrow) output line. The circuit is prototyped using 0.18μm CMOS technology using Cadence development tools and simulated using Spectre.||URI:||http://hdl.handle.net/10356/16726||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
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