Design and simulation of ternary logic gates using emerging electronic devices

Abstract

As information technology advances, the need to process an enormous amount of data has arisen. Thus, more advanced chips are being developed by shrinking transistor feature sizes to cope with the heavy-duty of data handling. However, traditional binary logic has gradually become insufficient, as it has been reaching the limit of dimensional scaling. Therefore, the multi-valued logic system has gained attention. In this project, ternary logic circuits including standard ternary inverter (STI), positive ternary inverter (PTI), negative ternary inverter (NTI), balanced and unbalanced half adders, balanced and unbalanced full adders, carry ripple adder (CRA), carry look-ahead adder (CLA), as well as multiplier are designed based on the Quine-McCluskey algorithm. Their performances are simulated and tested using HSPICE tools. Overall, the proposed ternary circuits in the project have shown improved power-delay-product (PDP) values compared to their binary counterparts.