Design of a single balanced mixer in CMOS for applications at 5.2GHz

Abstract

Frequency mixers have had a profound impact on modern-day technology, particularly in the areas of wireless communication, radar systems, and medical imaging. They have made it possible for us to transmit and receive signals over long distances, detect and locate objects, and obtain detailed images of the human body. To this day, it is still the mission of the industry to aim improve the device through minimalizing space usage whilst maintaining or enhancing device performance. This project aims to design Single Balanced Mixer in 65nm CMOS technology. The designing phase of this mixer will be done using Cadence Virtuoso in TSMC 65nm technology to design and simulate the performance of the Single Balanced Mixer. This study will include the designing phase from designing the schematic diagram to creating its layout drawing aiming for a smaller design which could potentially increase the overall performance of the system.