The design of a successive approximation register (SAR) ADC for BMS

Abstract

In this project, a 10-bit SAR ADC is proposed and designed. The ADC is set to use a power supply of 2.5V and have a sampling frequency of 10MHz, allowing for a signal input frequency of up to 5MHz to be sampled. The range of signal conversion of the ADC is from 0 to 1.25V with a digital output signal of 10 bits, allowing for 1024 discrete level of signal conversion. The entire circuit is designed using TSMC’s 55nm CMOS technology. The Cadence® Virtuoso® Analog Design Environment (ADE)-L is used for schematic design, as well as circuit simulation. The SAR ADC utilizes synchronous clocking for its digital blocks, which consist of a 10-bit control unit, a 10-bit digital register, as well as a digital output latch. All of which utilizes a D-Flip Flop for bit storage. The analog component consists of a strongArm latch comparator, a charge redistribution digital to analog converter (CDAC), and a voltage reference.