Design and simulation of CMOS-based ternary logic arithmetic circuits

Abstract

With the progression of information technology, there has been a burgeoning demand for processing voluminous quantities of data. In the contemporary era of information and data, the traditional binary logic system has become increasingly insufficient in coping with the vast quantities of data generated incessantly. Thus, ternary systems has garnered considerable interest due to the mounting challenges associated with binary CMOS system design and the need to meet the demands of contemporary end-users . In this project, we designed an array of ternary inverters and various algorithmic gates. Following the successful design phase, we proceeded to assess critical performance metrics, such as power consumption, propagation delay, and Power-Delay Product (PDP). Finally, we designed a layout of a ternary inverter.