Research and design of sub-T band radio frequency integrated circuit frequency multipliers

Abstract

This dissertation mainly working on the study of CMOS millimetre-wave frequency multipliers. By reviewing the literature on global frequency multiplier research, the methodology of frequency multiplier design is outlined and the basic theory of frequency multiplier design is explanation. Finally, a 250 GHz frequency doubler based on 65 nm CMOS process is designed. The design of the frequency doubler uses a classical structure called push-push to fullfill a 250 GHz frequency doubler, which shows a wide output signal bandwidth and effectively improves the doubling gain and harmonic rejection. The stability factor is showed by pre-simulation results of the frequency doubler and it is much higher than 1 in the operating frequency range. In other words, the circuit is absolutely stable, with a frequency doubling gain of -13.21 to -12.33 dB and a spurious rejection ratio of more than 15 dBc at an input frequency of 115-140 GHz. The second harmonic signal at the output is relatively flat, with a 3 dB bandwidth of 98 to 147 GHz and a relative bandwidth of 39.2%. This frequency doubler can improve the harmonic rejection capability and at the same time obtain a relatively wide output signal bandwidth, which can meet the requirements of 250GHz broadband communication system.