Quantum correction hardware accelerator design on FPGA

Abstract

As the size of problem systems in various fields continues to grow, classical computing is subject to increasing challenges. However, since quantum has a superposition feature, quantum computing with high computational power promises to quickly enhance the computational process. As a result, Quantum computing has emerged as a promising technology for solving computationally challenging problems that are beyond the capabilities of classical computers. In this report, we present the design and simulation of a quantum readout processing block, which consists of a pipeline accumulator, a Direct Digital Frequency Synthesizer (DDFS) unit based on phase accumulator and CORDIC algorithm,and a qubit state decision unit based on homodyne mixing. The quantum readout processing block is a critical component of a quantum computer, as it is responsible for reading and processing the ADC data, and then determining the qubit state. The architecture of the to read and process the ADC data then determine the qubit state is reported in this final year project report. This report focuses on the error analysis for different bitwidths and iterations of the CORDIC, in order to provide insights on their influence on the hardware cost, and further proceed error analysis on homodyne mixing and state decision. In order to reduce hardware consumption, the bitwidths and number of iterations are reduced, which further leads to a decrease in accuracy. The simulation results showed that under different bitwidths and iterations, the error of the sine/cosine wave and the error of the iq value as compared to the ideal case, and in this case, it is judged whether the state decision has changed or not. At the same time, according to the simulation results, it can be seen that under the required error conditions, the number of bitwidth and iteration and hardware consumption.