A fully integrated low dropout regulator for partial discharge detection applications

Abstract

The power management unit, such as the low dropout regulator (LDO), plays an important role in the integration of the DAQ chips designed for detecting the partial discharge events in the power systems. A suitable LDO in this application should be capable of providing high-quality supply voltage over a wide load range while making fast responses against load variations. However, due to stability issues, it is often challenging for the fully integrated regulator design to achieve both features simultaneously. Therefore, in this dissertation, a flipped voltage follower (FVF) based LDO with a novel pole-tracking frequency compensation technique and transient enhancing structure is proposed to overcome these obstacles.

The suggested FVF-LDO is built in TSMC 65 nm process with a 1 V power supply and 200 mV dropout voltage. This regulator exhibits a 95 uA to 122 uA quiescent current when supporting the load current ranging from 0.1 mA to 100 mA. With the compensation topology, an over 60 degree phase margin is obtained across the entire load range. And in full load operation, a low-frequency power supply rejection (PSR) of -59 dB and a 0.85 mV/V line regulation are achieved with a 100 pF on-chip capacitor. Furthermore, the proposed LDO presents 88 mV voltage displacement for the maximum load variation with 100 ns edge time and can settle to 1% accuracy within 640 ns with a 40 MHz unity gain bandwidth.