Please use this identifier to cite or link to this item:
https://hdl.handle.net/10356/170099
Title: | A 6-Gb/s PAM-3 transceiver with background time-varying offset sensing and compensation | Authors: | Kim, Ju Eon Yoon, Dong-Hyun Song, Junyoung Baek, Kwang-Hyun Choi, Jung-Hwan Kim, Tony Tae-Hyoung |
Keywords: | Engineering::Electrical and electronic engineering | Issue Date: | 2023 | Source: | Kim, J. E., Yoon, D., Song, J., Baek, K., Choi, J. & Kim, T. T. (2023). A 6-Gb/s PAM-3 transceiver with background time-varying offset sensing and compensation. IEEE Solid-State Circuits Letters, 6, 85-88. https://dx.doi.org/10.1109/LSSC.2023.3260197 | Journal: | IEEE Solid-State Circuits Letters | Abstract: | Time-varying offset such as transistor aging increases mismatches of differential pairs at pulse amplitude modulation (PAM)-3 transceivers, exacerbating signal integrity. To tackle this issue, this letter proposes a time-varying offset sensing and compensation technique for a PAM-3 transceiver. The proposed compensation algorithm continuously monitors the offset by detecting faulty sensing output patterns and generates optimal reference voltage for the single-to-differential amplifier and decision feedback equalizer to cancel out the offset. The proposed 6-Gb/s PAM-3 transceiver was fabricated in 65-nm CMOS technology. The proposed offset compensation technique improves the worst-case eye-openings by 38% compared to the baseline design. | URI: | https://hdl.handle.net/10356/170099 | ISSN: | 2573-9603 | DOI: | 10.1109/LSSC.2023.3260197 | Schools: | School of Electrical and Electronic Engineering | Rights: | © 2023 IEEE. All rights reserved. | Fulltext Permission: | none | Fulltext Availability: | No Fulltext |
Appears in Collections: | EEE Journal Articles |
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