A digital bit-reconfigurable versatile compute-in-memory macro for machine learning acceleration

Abstract

This brief proposes a digital versatile SRAM-based computing-in-memory (CIM) macro with reconfigurable precision from 1-bit to 16-bit and programmable mathematical functions, including addition and multiplication. The proposed CIM macro supports 116-bit weight-stationary addition (WSA) and operands-stationary addition (OSA), and 18-bit bit-serial multiplication (BSM). The proposed versatile CIM macro accelerates various machine learning algorithms such as convolutional neural networks (CNNs) and self-organizing maps (SOMs). A test chip was fabricated in 65nm CMOS technology and achieved an energy efficiency of up to 40.7 TOPS/W for WSA (1-bit), 39.4TOPS/W for OSA (1-bit), and 84.1 TOPS/W for BSM (1-bit).