Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/17073
Title: Si nanowire based NVM : SONOS fabrication & characterization
Authors: Chen, Mincong.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
Issue Date: 2009
Abstract: A gate-all-around (GAA) non-volatile memory (NVM) SONOS fabricated on a vertical Si nanowire using CMOS compatible technology. Si vertical nanowires with height of 800nm and diameter as small as 20nm were explored. Without advanced lithography technology, the surrounding gate length can be controlled easily by etch back of sacrificial oxide. In this work, only gate length of 200nm was used. With the un-optimized SONOS gate stack, it was found that devices with 50nm vertical nanowire as the channel exhibited well-behaved memory characteristics, in terms of the P/E window, retention, and endurance properties. Nanowires with diameter smaller than 50nm tend to fall off during processes due to the high aspect ratio. Devices with nanowire diameter larger than 50nm showed large off-state current. The vertical Si nanowire based SONOS is promising for future multilevel memory structures 3-dimensionally, which will be an excellent candidate for low power and high density application.
URI: http://hdl.handle.net/10356/17073
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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