Please use this identifier to cite or link to this item:
https://hdl.handle.net/10356/170916
Title: | A dual-path subsampling PLL with ring VCO phase noise suppression | Authors: | Dong, Yangtao Boon, Chirn Chye Liu, Zhe Yang, Kaituo |
Keywords: | Engineering::Electrical and electronic engineering | Issue Date: | 2023 | Source: | Dong, Y., Boon, C. C., Liu, Z. & Yang, K. (2023). A dual-path subsampling PLL with ring VCO phase noise suppression. IEEE Transactions On Microwave Theory and Techniques. https://dx.doi.org/10.1109/TMTT.2023.3284279 | Journal: | IEEE Transactions on Microwave Theory and Techniques | Abstract: | This article presents a 2-GHz dual-path subsampling phase-locked loop (SSPLL) with ring voltage-controlled oscillator (VCO) phase noise suppression (PNS). In addition to the conventional subsampling charge pump (SSCP), a high pass path from the subsampling phase detector (SSPD) to the low-pass filter (LPF) is implemented in the proposed SSPLL. Due to this dual-path architecture, a new in-band zero and pole are introduced into the open-loop transfer function (zero frequency is smaller than the pole frequency), which extends the open-loop unit-gain bandwidth without sacrificing the phase margin. Consequently, the phase noise contribution of the ring VCO is suppressed while the loop stability is ensured. Meanwhile, the phase noise contribution of the high-pass path is negligible compared to the reference and ring VCO’s contribution. Measurement results show that the SSPLL’s closed-loop bandwidth is extended to around 6 MHz with a reference of 20 MHz and the jitter is reduced by 1.34× (from 3.52 to 2.63 ps) with a maximum noise suppression of 6.5 dB at the 1.1-MHz offset. The PNS path consumes 0.16 mW and no delay line or calibration is needed, which results in a relatively high FoMPNC value of 40.5 dB. | URI: | https://hdl.handle.net/10356/170916 | ISSN: | 0018-9480 | DOI: | 10.1109/TMTT.2023.3284279 | Schools: | School of Electrical and Electronic Engineering | Research Centres: | Centre for Integrated Circuits and Systems (CICS) VIRTUS, IC Design Centre of Excellence |
Rights: | © 2023 IEEE. All rights reserved. This article may be downloaded for personal use only. Any other use requires prior permission of the copyright holder. The Version of Record is available online at http://doi.org/10.1109/TMTT.2023.3284279. | Fulltext Permission: | open | Fulltext Availability: | With Fulltext |
Appears in Collections: | EEE Journal Articles |
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FINAL VERSION.pdf | 1.01 MB | Adobe PDF | ![]() View/Open |
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