Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/171735
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dc.contributor.authorHuai, Shuoen_US
dc.contributor.authorKong, Haoen_US
dc.contributor.authorLuo, Xiangzhongen_US
dc.contributor.authorLiu, Dien_US
dc.contributor.authorSubramaniam, Ravien_US
dc.contributor.authorMakaya, Christianen_US
dc.contributor.authorLin, Qianen_US
dc.contributor.authorLiu, Weichenen_US
dc.date.accessioned2023-11-06T07:29:34Z-
dc.date.available2023-11-06T07:29:34Z-
dc.date.issued2023-
dc.identifier.citationHuai, S., Kong, H., Luo, X., Liu, D., Subramaniam, R., Makaya, C., Lin, Q. & Liu, W. (2023). On hardware-aware design and optimization of edge intelligence. IEEE Design & Test, 40(6), 149-162. https://dx.doi.org/10.1109/MDAT.2023.3307558en_US
dc.identifier.issn2168-2356en_US
dc.identifier.urihttps://hdl.handle.net/10356/171735-
dc.description.abstractEdge intelligence systems, the intersection of edge computing and artificial intelligence (AI), are pushing the frontier of AI applications. However, the complexity of deep learning models and heterogeneity of edge devices make the design of edge intelligence systems a challenging task. Hardware-agnostic methods face some limitations when implementing edge systems. Thus, hardware-aware methods are attracting more attention recently. In this paper, we present our recent endeavors in hardware-aware design and optimization for edge intelligence. We delve into techniques such as model compression and neural architecture search to achieve efficient and effective system designs. We also discuss some challenges in hardware-aware paradigm.en_US
dc.description.sponsorshipNanyang Technological Universityen_US
dc.language.isoenen_US
dc.relationIAF-ICPen_US
dc.relationI1801E0028en_US
dc.relationNAP (M4082282/04INS000515C130)en_US
dc.relation.ispartofIEEE Design & Testen_US
dc.rights© 2023 IEEE. All rights reserved.en_US
dc.subjectEngineering::Computer science and engineeringen_US
dc.titleOn hardware-aware design and optimization of edge intelligenceen_US
dc.typeJournal Articleen
dc.contributor.schoolSchool of Computer Science and Engineeringen_US
dc.contributor.researchHP-NTU Digital Manufacturing Corporate Laben_US
dc.identifier.doi10.1109/MDAT.2023.3307558-
dc.identifier.scopus2-s2.0-85168725926-
dc.identifier.issue6en_US
dc.identifier.volume40en_US
dc.identifier.spage149en_US
dc.identifier.epage162en_US
dc.subject.keywordsComputational Modelingen_US
dc.subject.keywordsHardwareen_US
dc.description.acknowledgementThis work was supported in part by the RIE2020 Industry Alignment Fund—Industry Collaboration Projects (IAF-ICP) Funding Initiative as well as cash and in-kind contribution from the industry partner, HP Inc., through the HP-NTU Digital Manufacturing Corporate Lab under Grant I1801E0028 and in part by Nanyang Technological University, Singapore, through its NAP under Grant M4082282/04INS000515C130.en_US
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