Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/171880
Title: A novel design of power-efficient reconfigurable multiplier targeting at increasing the throughput of the CGRA
Authors: Li, Jiaxu
Issue Date: 2023
Publisher: Nanyang Technological University
Source: Li, J. (2023). A novel design of power-efficient reconfigurable multiplier targeting at increasing the throughput of the CGRA. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/171880
Abstract: In the dynamic world of artificial intelligence (AI) with escalating computational needs, the significance of edge computing has risen. Edge computing emphasizes local computations on devices, particularly using Software-Defined Chip (SDC) such as the Coarse-Grained Reconfigurable Architecture (CGRA), renowned for its superior energy efficiency and adaptable reconfiguration attributes. On an algorithmic front, edge computing's adaptability to computational precision has led to the widespread use of quantized AI models within the CGRA framework, aiming to further boost computational prowess and explore the new way to solve the bottleneck problem of computing power under the limit of Moore's Law. This research aims at increasing the throughput of the CGRA chip, and therefore introduces an innovative strategy to amplify power efficiency of the conventional multiplier, featuring its functionality of conducting parallel multiplications to replace the conventional multiplier inside the Process Element (PE). Comprehensive simulations using 40nm CMOS technology revealed that when using continuous short-bit multiplications workload as a testing benchmark, the throughput of PE saw a notable rise in comparison to the PCAE chip with the original Cadence IP multiplier. And after implementing the array multiplications application on the optimized CGRA, the throughput sees an improvement of 98% and 296% for 4-bit multiplications and 2-bit multiplications respectively. This improvement highlights the substantial enhancement in PE's performance with the integration of the suggested reconfigurable multiplier into the CGRA design, expecting for higher potential to deal with quantized AI models.
URI: https://hdl.handle.net/10356/171880
Schools: School of Electrical and Electronic Engineering 
Organisations: Institute of Microelectronics, A*STAR
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
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