The validation of high-performance QDI asynchronous pipeline circuit

Abstract

This dissertation pertains to the study of a comprehensive validation of the asynchronous (async) pipeline, utilizing a range of structures including multipliers and Finite Impulse Response (FIR) filters. The aim was to rigorously assess the async pipeline’s function, performance and efficiency. Our findings indicate that the async pipeline architecture can be combined in various forms and possesses inherent characteristics that make it particularly effective in eliminating glitches, a common issue in synchronous systems. This ‘no glitch’ feature underscores the async pipeline’s potential to enhance operational stability and reliability. Furthermore, our analysis reveals the async pipeline’s significant potential for low power consumption. By comparing the async pipeline with traditional synchronous models, especially in the context of complex computational tasks, we observed a marked improvement in energy efficiency. These results suggest that the async pipeline offers promising avenues for developing more energy-efficient and stable computing architectures which are particularly relevant in the design of advanced digital systems.