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https://hdl.handle.net/10356/174065
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DC Field | Value | Language |
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dc.contributor.author | Liang, Xuanyu | en_US |
dc.date.accessioned | 2024-03-14T05:52:26Z | - |
dc.date.available | 2024-03-14T05:52:26Z | - |
dc.date.issued | 2024 | - |
dc.identifier.citation | Liang, X. (2024). AES encryption with advanced key expansion. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/174065 | en_US |
dc.identifier.uri | https://hdl.handle.net/10356/174065 | - |
dc.description.abstract | As information technology continues to rapidly advance in current society, information security is becoming increasingly important for personal privacy. The Advanced Encryption Standard (AES) is an efficient method to help the public protect their personal information. In order to improve the AES performance in securitythis thesis focuses mainly on the hardware implementation of AES-192 encryption. This thesis summarizes several aspects that can improve AES-192 hardware implementation performance , particularly through improvements in the key expansion section, thereby increasing AES encryption security. The main contribution of this thesis is the implementation of the AES-192 encryption for both software and hardware. It firstly simulates the correctness of the design in VCS and test its correctness. After the correctness is evaluated, this thesis then examines the power consumption and throughput of the design. Then it implements AES-192 on Field Programmable Gate Arrays (FPGA) and tests its correctness after the design is complete. It is evident that the AES-192 Encryption Design is correct in both software and hardware implementation. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Nanyang Technological University | en_US |
dc.subject | Engineering | en_US |
dc.title | AES encryption with advanced key expansion | en_US |
dc.type | Thesis-Master by Coursework | en_US |
dc.contributor.supervisor | Lin Zhiping | en_US |
dc.contributor.school | School of Electrical and Electronic Engineering | en_US |
dc.description.degree | Master's degree | en_US |
dc.contributor.research | Centre for Integrated Circuits and Systems | en_US |
dc.contributor.supervisoremail | EZPLin@ntu.edu.sg | en_US |
item.grantfulltext | embargo_restricted_20260415 | - |
item.fulltext | With Fulltext | - |
Appears in Collections: | EEE Theses |
Files in This Item:
File | Description | Size | Format | |
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Liang_xuanyu_revised_final1.pdf Until 2026-04-15 | 3.78 MB | Adobe PDF | Under embargo until Apr 15, 2026 |
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