Research and design of high-speed column ADC for CMOS image sensor applications

Abstract

As an integral part of the vision system, image sensors find extensive use in sectors such as digital photography, security surveillance, automobile driving, and medical imaging. As an important interface between photoelectric signals and digital images, the imaging quality is directly influenced by the functionality of the analog-to-digital converter (ADC). In image sensor applications, ADCs are typically arranged in a column readout configuration to strike an excellent balance between factors such as the fill factor, conversion speed, quantization accuracy, and area overhead. ADCs serve as the pivotal point in the analog-to-digital conversion process for CMOS image sensors (CIS). They are designed according to the demands of large pixel arrays and rapid imaging prevalent in CMOS image sensors. Currently, there are three categories of ADCs commonly employed in CISs: pixel-level ADCs, chip-scale ADCs, and column one. Among these, column-level ADCs provide a favorable balance between conversion speed, chip area, and power loss. They are particularly well-suited for application in high-resolution, high-frame-frequency CISs. Hence, the primary objective of this paper is to examine and develop column-based ADCs specifically for CISs.

First, by comparing several commonly used column-based ADC structures in CISs, the new 10-bit single-slope ADC presented in this paper is implemented using a unique ADC technique, with the conversion process being split into two parts: the time-to-digital converter (TDC) and the analog-to-time converter (ATC). In ATC, the ramp generator is realized by using the structure of the current source discharging the capacitor to ensure the time accuracy of the ramp, and the comparator is realized by a three-stage cascade to eliminate the effect of the intermodulation. In TDC, this paper adopts a two-step quantization method, in which the 6-bit coarse quantization is realized by a gated ring oscillator and a counter to save area, and the implementation of the 4-bit fine one is achieved through the utilization of a vernier delay line (VDL) in order to guarantee both high accuracy and speed. Secondly, this paper proposes a correction circuit specifically designed to counteract the error caused by mismatching delay times between the coarse and fine quantization stages in TDC, a method that overcomes the drawbacks of traditional approaches, such as doubling the area or time of fine quantization and achieves correction with a simpler circuit structure. Subsequently, specific design methods are proposed for each module in the system, which mainly includes a slope generator, a comparator, a gated ring oscillator, a counter, a phase-locked loop, a delay-locked loop, a time amplifier, peripheral circuits, and other parts. Finally, the overall circuit is tested and verified.

The 0.65 µm CMOS process is used in the design, and Cadence simulation software is utilized. The ADC’s key modules and its overall elevator simulation are performed using this program. The circuit is powered by 2.5 volts. The requirements for converting a 400 MHz frequency signal to digital are fulfilled by adopting a two-step quantization method to achieve 10-bit high-precision quantization.