Exploring network-on-chip architectures: performance optimization and experimental analysis

Abstract

The rapid evolution of technology has given rise to a variety of new applications that require enhanced computational capabilities. Multi-core processors are therefore necessary in meeting these demands, yet optimizing their interconnectivity remains a challenge. The existing Network-On-Chip (NoC) architectures may face limitations in efficiently supporting these applications. This becomes particularly significant given more on-chip cores and the integration of cache coherence protocols (CCPs). These factors can lead to increased latency and energy overhead in network communication, necessitating the development of a novel NoC architecture. Hence, the project aims to address this critical issue by designing an innovative NoC architecture, specifically focusing on accommodating the growing number of cores in modern processors. However, before doing so, it is imperative to conduct a comprehensive study on the present NoC landscape. This analysis will provide valuable information on the current challenges faced and identify areas for improvement. By leveraging this understanding, we hope to improve the performance, scalability, and power efficiency of multi-core processors through the proposed NoC architecture. This ensures that the processors can effectively adapt to the diverse and constantly changing needs of emerging applications.