CT sigma delta ADC for audio applications

Abstract

In this report, a system level simulation of low-power fourth order CT-∑∆ modulator in Matlab and circuit level design of first integrator in Cadence is presented. That modulator is to be used in audio applications and sensor analog front end and design is proposed to achieve minimum requirement of ENOB of 14.6 bits, SNR of 90dB within a 25 kHz signal bandwidth with oversampling ratio of 64. On the system level, a low-power, mainly feed-forward architecture is used to realize the loop filter. Feed-in branches are added and optimized to eliminate the out-of-band peaking in the signal transfer function. Firstly modeling of fourth of in DT was performed without non-idealities and after that modeling DT to CT conversion was done after coming out the transfer function which was written into codes. Ideal system level simulation of CT was done prior to CT SDM with non-idealities. The non-idealities simulation was extensively run to check how much the overall system can take non-idealities behaviors of gain, gain bandwidth, slew-rate and linearity while meeting performance requirements. Enhanced CT non-idealities SDM was designed which is up to the circuit level. Prior to circuit design, MOS device characterization was done to understand how MOS works so that it enhances designing of circuit. The circuit level simulation is done in 0.18µm CMOS technology. Two-stage differential amplifier with class-AB output stage is used to implement low-power active RC integrators. The op-amp has 70dB gain with phase margin of 68ْ. The test results show that the first integrator draws less than 20µA from the 1.2 V supply voltage.